Multi-drain semiconductor power device and edge-termination structure thereof

ABSTRACT

An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

PRIORITY CLAIM

The present application claims priority to Italian Patent Application No. TO2008A000999, filed Dec. 29, 2008, which application is incorporated herein by reference in its entirety.

TECHNICAL FIELD

An embodiment of the present invention relates to a semiconductor power device of a multi-drain type and to a corresponding edge-termination structure.

BACKGROUND

In the last few years, a wide range of solutions have been developed for improving the efficiency of semiconductor power devices, and in particular for obtaining an increase of the breakdown voltage and a decrease of the output resistance.

For example, U.S. Pat. No. 6,228,719, U.S. Pat. No. 6,300,171, U.S. Pat. No. 6,404,010, and U.S. Pat. No. 6,586,798, which are incorporated by reference, describe vertical-conduction semiconductor power devices of the multi-drain (MD) type, wherein, within an epitaxial layer forming part of a drain region having a given type of conductivity, charge-balance columnar structures are provided, having opposite conductivity. These structures have a dopant concentration substantially equal and opposite to the dopant concentration of the epitaxial layer in such a way as to provide a substantial charge balance. Charge balance enables high breakdown voltages to be obtained, and moreover the high concentration that the epitaxial layer can consequently assume enables a low output resistance (and reduced losses in conduction) to be achieved.

In order to manufacture the columnar structures, a sequence of steps of growth of epitaxial layers of a first conductivity, for example of an N type, is envisaged, each step being followed by an implantation of dopant of the second conductivity, in the example of a P type. The implanted regions are stacked and subjected to a subsequent process of diffusion of the dopant atoms so as to give rise to uniform columnar structures.

Next, body regions of the power device are formed in contact with the columnar structures, in the active region, in such a way that the columnar structures constitute an extension of the body regions within the drain region.

The evolution of this technology has shown a progressive increase in the density of the elementary strips forming the devices in order to increase further the charge concentration of the epitaxial layer and obtain devices that, given the same breakdown voltage (substantially linked to the height of the columnar structures), would present a lower output resistance. On the other hand, however, the increase in the density of the elementary strips has led to a reduction of the thermal budget of the devices and a corresponding increase in the number of steps of epitaxial growth, and hence an increase in the manufacturing costs and time and in the defectiveness intrinsically linked to the epitaxial growth.

Alternative techniques have hence been developed in order to obtain the charge-balance structures, which envisage, for example, formation of trenches within the epitaxial layer and subsequent filling of the same trenches with semiconductor material appropriately doped to achieve the charge balance. For example, in patent applications WO 2007/116420 and WO 2007/122646, which are incorporated by reference, techniques are described for obtaining charge-balance structures in electronic power devices, which envisage the formation of trenches and filling thereof without any residual defectiveness via a particular technique of non-selective epitaxial growth performed in the same trenches.

It is also known that the formation of efficient edge-termination structures may be a key point for ensuring proper operation of the power devices. In fact, it is at the edge areas (i.e., the areas surrounding the active area in which the electronic components are provided) that the highest number of breakdown phenomena occurs on account of the thickening of the electric field lines due to the presence of discontinuities, such as sharp edges or the curvature of the doped regions. Edge terminations have the function of reducing the intensity of the electric field locally so as to prevent peaks of intensity at the edges.

FIGS. 1-4 (which are not drawn to scale, as the subsequent figures are also not to scale) show an example of an edge-termination structure of a known type, for a vertical-conduction charge-balance power device. In particular, FIG. 1 shows a schematic and simplified top plan view, whilst FIGS. 2, 3 and 4 show cross sections taken along lines II-II, III-III and IV-IV indicated in FIG. 1, respectively.

The power device, designated by 1, is formed in a die 2 of semiconductor material, for example silicon. The die 2 has, in top plan view, a generically rectangular or square shape; the borders and edges of the die 2 correspond to the so-called “scribe lines” (designated by LT), at which the starting wafer of semiconductor material has been cut. In the die 2 it is possible to define a peripheral portion 2 a, adjacent to the scribe lines, and a central portion 2 b, in which the power device 1 is physically provided.

The die 2 comprises a substrate 3 having a first type of conductivity, for example of an N⁺⁺ type, and an epitaxial layer 4, formed on the substrate 3, also having the first type of conductivity, in the example of an N type. Within the epitaxial layer 4 it is possible to distinguish an active area 4 a, designed to house elementary electronic components 50 (in the example, MOS transistors) of the power device 1, and an edge area 4 b, designed to house an edge-termination structure of the device and adjoining the peripheral portion 2 a of the die 2. In particular, the epitaxial layer 4 constitutes a common drain surface region for the plurality of elementary electronic components 50 (the MOS transistors) forming the power device 1.

The edge-termination structure comprises a ring region 5, in particular a region doped with a second type of conductivity, of a P type, with low concentration, for example, lower than 10¹⁶ at/cm³, formed in a surface portion of the epitaxial layer 4. The ring region 5 is provided within the edge area 4 b, surrounds the active area 4 a completely (forming a ring around it), and has an area of superposition with a peripheral portion of the same active area 4 a. In particular, the ring region 5 has a rounded-off and curved profile in such a way as to reduce local concentrations of the field lines.

Charge-balance structures 7 (which have in cross section a column conformation, see in particular FIGS. 2-4) traverse the epitaxial layer 4 substantially throughout its thickness, stopping at a certain distance from the substrate 3, both at the active area 4 a and at the ring region 5 in the edge area 4 b. The charge-balance structures 7 are, for example, obtained through successive steps of epitaxial growth and implantation of dopant atoms in order to obtain stacked doped regions, and through a final step of diffusion of the dopant atoms.

The charge-balance structures 7 follow the layout of the regions in which they are formed, and are constituted by doped regions having the second type of conductivity (P) and a doping level such as to create a substantial charge balance. In particular, in the active area 4 a the charge-balance structures 7 are constituted (in plan view, see FIG. 1) by first strips 7 a, having a substantially rectilinear extension, parallel to one another and to a first side of the die 2 (and to a first axis x), which repeat periodically and at substantially the same distance in a direction parallel to a second side of the die 2 (and to a second axis y, orthogonal to the first axis x). Instead, in the edge area 4 b the charge-balance structures 7 follow the pattern and the profile of the ring region 5, within which they are housed, and are made up of second strips 7 b, once again parallel to and set at substantially the same distance from one another, each of which is constituted by: a first rectilinear portion parallel to the first side of the die 2 (and to the first axis x); a second rectilinear portion parallel to the second side of the die 2 (and to the second axis y); and a curved connecting portion between the first rectilinear portion and the second rectilinear portion (in particular having substantially the same radius of curvature as the ring region 5).

In particular, given their columnar extension in the thickness of the epitaxial layer 4, the charge-balance structures 7 constitute vertical walls or diaphragms extending in strips within the same epitaxial layer 4. In addition, in current design rules, the number of the second strips 7 b that occupy the ring region 5 is determined by the dimension of the ring and by the pitch (in terms of spacing and size) of the first strips 7 a in the active area 4 a.

Body wells 9 are present within the active area 4 a, having the second type of conductivity (P) and contacting each first strip 7 a of the charge-balance structures 7, at the surface portion of the epitaxial layer 4. In particular, the first strips 7 a constitute extensions of the body wells 9 within the drain region in the epitaxial layer 4. Source regions 10, having the first type of conductivity (N), are provided inside each body well 9. In particular, in the area of superposition between the active area 4 a and the ring region 5, the outermost body wells 9 join the same ring region 5. In addition, in the edge area 4 b, the second strips 7 b of the charge-balance structures 7 are joined to one another by the ring region 5.

The power device 1 further comprises, on the surface of the epitaxial layer 4, a first dielectric region (for example, made of silicon oxide) 12, having a greater thickness at the edge area 4 b and a smaller thickness in the active area 4 a, where it provides the gate-oxide regions of the elementary electronic components 50. A gate region (made of polysilicon or other conductive material) 14 is provided on the first dielectric region 12; on the gate-oxide regions, the gate region 14 provides the gate structures of the elementary electronic components 50.

In addition, a second dielectric region (for example, made of field oxide) 15 covers the first dielectric region 12 and the gate region 14. The second dielectric region 15 is traversed, at the edge area 4 b, by a gate metal contact 18, designed to contact the gate region 14. In addition, the second dielectric region 15, the first dielectric region 12, and the gate region 14 are traversed, in the active area 4 a, by a source metal contact 16, extending to contact and short-circuit the source regions 10 and the body wells 9. At the periphery of the edge area 4 b (adjacent to the peripheral portion 2 a of the die 2), the surface of the epitaxial layer 4 is left exposed so as to enable an equipotential-ring (EQR) metal contact 19 to contact a doped region 20, in particular a doped region having the first type of conductivity (N), provided in the surface portion of the epitaxial layer 4. The doped region 20 is set at a distance from the ring region 5, and has the same ring layout as the latter, surrounding it completely. The contact region 20 has the function of bringing to the surface the drain potential so as to limit horizontally the electric field lines in reverse biasing.

In analysing the cross sections of FIGS. 2-4, it is to be noted in particular that the cross section of FIG. 2 is taken in a direction transverse to the direction of extension of the charge-balance structures 7, and that the cross sections of FIGS. 2 and 3 are both taken along the direction of extension of the charge-balance structures 7, but on the outside and on the inside, respectively, of a first strip 7 a.

It has been shown that power devices of the type described, although having considerable advantages as compared to traditional solutions, may be subject to phenomena of early breakdown that can jeopardize their performance or, in the worst case, prevent their subsequent use (i.e., destroy them).

SUMMARY

An embodiment of the present invention overcomes the above drawbacks and further improves a charge-balance power device.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present disclosure, one or more embodiments are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

FIG. 1 is a schematic and simplified top plan view of a portion of a power device of a known type, in particular corresponding to an edge-termination structure;

FIGS. 2, 3, and 4 show cross sections of the device of FIG. 1, taken along lines II-II, III-III, and IV-IV of FIG. 1, respectively;

FIG. 5 shows an IN plot representing the reverse breakdown characteristic of the device of FIG. 1;

FIG. 6 shows a microscope photograph of the result of an emission-microscopy (EMMI) analysis on the portion of the power device of FIG. 1;

FIG. 7 a is a schematic and simplified top plan view of a power device according to an embodiment of the present invention;

FIG. 7 b is a top plan view of a portion of the device of FIG. 7 a, in particular regarding an edge-termination structure thereof;

FIGS. 8, 9 and 10 show cross sections of the device of FIGS. 7 a and 7 b, taken along lines VIII-VIII, IX-IX, and X-X of FIG. 7 b, respectively;

FIGS. 11-12 show plots representing the breakdown characteristics of the device of FIGS. 7 a and 7 b;

FIG. 13 shows a microscope photograph of the result of an EMMI analysis on the portion of the power device of FIG. 7 b;

FIGS. 14 and 15 show top plan views similar to that of FIG. 7 b, regarding further embodiments of the present invention;

FIG. 16 shows a cross section of the power device shown in FIG. 15, taken along the line XVI-XVI; and

FIGS. 17 and 18 show top plan views similar to that of FIG. 7 b, regarding further variant embodiments of the present invention.

DETAILED DESCRIPTION

It has been discovered and verified experimentally that the critical features of early breakdown afflicting the multi-drain power devices of the type previously described derive principally from the presence of discontinuities in the charge balance occurring within the edge area 4 b, and specifically in the ring region 5.

In particular (see again FIG. 1), these discontinuities occur at the joining points between the charge-balance structures 7 in the active area 4 a and those in the edge area 4 b, and more particularly in the contact points between the first strips 7 a and the second, innermost, strip 7 b (i.e., the one closest to the active area 4 a), at which the charge may not be balanced and an excess of charge occurs. In detail, two types of intersection zones with marked charge unbalancing are generated: areas that in top plan view can be defined as “cuspidal”, designated by P_(C) in FIG. 1, at the intersection between a first set of first strips 7 a and the curved portion of the aforesaid second, innermost, strip 7 b; and areas that in top plan view are T-shaped, designated by P_(T) in FIG. 1, at the intersection between a second set of first strips 7 a and the second rectilinear portion of the second, innermost, strip 7 b.

These areas of excess of charge are a source of early triggering of breakdown having a triangular reverse-biasing characteristic, as shown in FIG. 5, whatever the number of the second strips 7 b that are present in the ring region 5.

The early triggering phenomena are moreover highlighted by the EMMI analysis shown in FIG. 6, regarding the same portion of device of FIG. 1, in which evident light emission phenomena are visible at the areas with higher charge unbalancing (cuspidal areas P_(C)).

Furthermore, it is noted (reference may be made to the cross sections of FIGS. 2-4) that the sections of the edge area 4 b, in a direction orthogonal or parallel to the direction of extension of the first strips 7 a, are different from one another, due to the asymmetry introduced in the structure by the arrangement of the second strips 7 b in the ring region 5, in particular in terms of the local charge balance that it is possible to obtain and of the number of charge-balance structures 7 joined to the ring region 5.

In order to overcome these critical features, an embodiment of the present invention envisages a different configuration of the charge-balance structures, such that the charge-balance structures occupy substantially uniformly and without any substantial discontinuity the entire area of the power device.

In detail, and as is shown in FIGS. 7 a and 7 b, where the same reference numbers are used for representing elements similar to others described previously, the charge-balance structures, here designated by 7′, of the power device, here designated by 1′, comprise strips extending parallel to one another over the entire area of the die 2, and in particular throughout the active area 4 a (first strips 30 a) and throughout the edge area 4 b (second strips 30 b), without any mutual intersection. In addition, the strips 30 a, 30 b extend also to the peripheral portion 2 b of the die. The strips 30 a, 30 b extend, for example, parallel to the first side of the die 2 and to the first axis x, repeating periodically along the second axis y, at a substantially uniform distance of separation. In particular, the charge-balance structures 7′ do not follow in this case the layout of the ring region 5. It is to be noted that the first strips 30 a extend from the active area 4 a into the edge area 4 b, and also that the first, outermost, strip 30 a (i.e., the one closest to the edge area 4 b) is parallel to the adjacent second, innermost, strip 30 b (i.e., the one closest to the active area 4 a), without intersecting it throughout its extension.

This arrangement makes it possible to avoid discontinuity areas in the charge balance (in particular the cuspidal areas within the ring region 5), that have been shown to be at the origin of the points of local charge unbalancing in the epitaxial layer 4. In particular, the fact that all the charge-balance structures 7′ extend in a parallel way means that high electric field is always sustained by parallel “walls” of opposite charge, without intersecting structures that may locally induce an increase in the electric field.

The sections of the edge area 4 b, in a direction orthogonal or parallel to the direction of extension of the strips 30 a, 30 b, as shown in FIGS. 8-10, are in this case clearly equivalent in terms of the local charge balance that it is possible to obtain given that all the strips of the charge-balance structures 7′ extend parallel to one another, and in particular demonstrate how charge balance is obtained in the edge area 4 b in a way substantially similar to the active area 4 a.

It has been shown experimentally that the structure described, with the consequent elimination of local singularities, makes it possible to inhibit triggering of early breakdown. In this regard, FIG. 11 shows the resulting IN characteristic of the power device 1′, whilst FIG. 12 shows the comparison between the evolutions of the normalized breakdown voltage BVdss (breakdown voltage between drain and source with the gate set at ground potential) as a function of the net charge φ_(n) (charge of a P type minus charge of an N type) given in arbitrary units (a.u.), in the power device 1′ according to an embodiment of the present invention (solid line) and in a traditional device (dashed line). The shift observed experimentally of the peak of BVdss (that should ideally correspond to the charge balance, Φ_(n)=0), indicates that the local unbalancing in the structure may induce clamping of the maximum breakdown value.

An optimization of the layout in the edge area 4 b may enable elimination of this structural clamping in the breakdown voltage.

Also the EMMI analysis in breakdown conditions (FIG. 13) confirms the previous results, highlighting the presence of a substantially uniform emission between the strips of the charge-balance structures 7′.

As is shown in FIG. 14, a different embodiment of the present invention envisages that the strips 30 a, 30 b of the charge-balance structures 7′ do not extend throughout the entire surface of the die 2, but stop inside the edge area 4 b, before reaching the peripheral portion 2 a of the die 2. For example, the strips 30 a, 30 b interrupt beyond the ring region 5, in an intermediate point between the ring region 5 itself and the EQR metal contact 19 and the corresponding doped region 20. In particular, beyond the intermediate point there is no presence either of prolongations of the first strips 30 a or prolongations of the second strips 30 b, or of the same second strips 30 b.

A further embodiment of the present invention, shown in FIG. 15 (in top plan view) and in FIG. 16 (in a section transverse to the direction of extension of the strips 30 a, 30 b), further envisages the possibility that the edge-termination structure of the power device 1′ does not comprise the ring region 5 in the edge area 4 b. In the example shown, the strips 30 a, 30 b extend again parallel to one another and in a uniform way, over the entire area of the die 2, in the active area 4 a and in the edge area 4 b of the epitaxial layer 4. This embodiment may solve the problem of “charge unbalancing” induced by the ring region 5, in the cases where it is possible to verify that the accumulation of charges due to the presence of points with high electric field (which are no longer eliminated by the ring region) does not lead to a significant decrease in reliability. In fact, the ring region 5 introduces a surface charge at the edge area 4 b, which adds (with its sign) to the charge present in the charge-balance structures, consequently introducing in the proximity of the surface a certain local lack of uniformity in the charge balance.

Advantages of the semiconductor power device and of the corresponding edge-termination provided according to one or more embodiments of the present invention are clear from the foregoing description.

In particular, an embodiment removes, in multi-drain power devices basing their operation on charge balance in the epitaxial layer operating as extension of the drain, any discontinuity in the charge balance and consequently early breakdown phenomena, rendering the breakdown characteristic hard. The periodic and uniform structure of the charge-balance structures is maintained also in the edge region of the power device, providing a substantial charge balance in the drain region not only in the active area but also at the edge, and preventing the edge-termination structure from introducing significant singularities and significant local excesses of charge. In particular, the improvement of the performance in reverse biasing enables improvement of the industrialization of the process and the quality and reliability of the final devices produced.

Thanks to charge balancing, it is also possible to obtain values of resistivity of the epitaxial layer lower than 2 Ω·cm, and values of inhibition voltage comprised between 100 and 1500 V, as the thickness of the epitaxial layer varies.

Finally, it is clear that modifications and variations may be made to what is described and illustrated herein, without thereby departing from the scope of the present disclosure.

In particular, as is shown in FIG. 17 in an embodiment, a first spacing d₁ may be provided in the active area 4 a between the first strips 30 a, and a second spacing d₂, different from the first, between the second strips 30 b in the edge area 4 b. In the example shown, the distance between the first strips 30 a is greater than the distance between the second strips 30 b (but also the opposite solution may be adopted, d₂>d_(i)).

As is shown in FIG. 18, in an embodiment the strips 30 a, 30 b may have a different size (in particular, a different width L in a direction transverse to their main direction of extension) in the active area 4 a with respect to the edge area 4 b. For example, the first strips 30 a may have a transverse dimension L₁, and the second strips 30 b a second transverse dimension L₂, smaller than the first one (once again, the opposite solution may be alternatively adopted, L₂>L₁).

In particular, the aforesaid alternative embodiments may make it possible to afford greater margins of freedom in redefining the “design rules” in order to offset the charge unbalancing induced by the ring region 5 (in the case where it is not possible or desirable to eliminate it in order not to risk reliability problems), optimizing the size and spacing of the strips of the charge-balance structures in the edge area 4 b.

Furthermore, in an embodiment, the charge-balance structures 7′, instead of extending only within the epitaxial layer 4, may also reach the substrate 3 and terminate within the same substrate 3.

Clearly, different techniques may be used for obtaining the charge-balance columnar structures. For example, as described in patent application No. WO 2007/006503, which is incorporated by reference, the successive steps of epitaxial growth and implantation for creating superimposed implanted regions, instead of being designed to form the columnar structures, may be designed to form regions which are to define, between one another, the charge-balance columnar structures. Alternatively, as described in patent application No. EP-A1-1911075, which is incorporated by reference, it is possible to envisage successive superimposed implantations (in corresponding regions of epitaxial growth) to provide both the charge-balance columnar structures and the regions of opposite conductivity set between the same columnar structures. Alternatively, it may be possible to use the non-selective technique of epitaxial growth within trenches, substantially as described in the aforesaid patent applications Nos. WO 2007/116420 and WO 2007/122646, which are incorporated by reference.

One or more of the embodiments described may also be used, with the appropriate small modifications, to obtain a generic charge-balance power device (for example, a bipolar diode, a Schottky diode, a BJT, an IGBT, etc.) and the corresponding edge-termination structure. In particular, it is clear that, in the case, for example, of a diode power device, the epitaxial region constitutes an extension of a cathode terminal (even though usually also this power device is identified by the term “multi-drain”). Furthermore, it is evident that it is possible to obtain dual structures in which the charge balance is provided by means of formation of columnar structures with N doping in an epitaxial layer with P doping.

From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. 

1. A semiconductor power device comprising: a structural body made of semiconductor material having a first conductivity and provided with an active area, housing one or more elementary electronic components, and with an edge area externally delimiting said active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to said first conductivity, extending through said structural body both in said active area and in said edge area, in order to create a substantial charge balance therein, wherein said charge-balance structures are constituted by columnar walls extending in strips parallel to one another, without any mutual intersections, in said active area and in said edge area.
 2. The device according to claim 1, wherein first strips of said charge-balance structures extend without any discontinuity from said active area into said edge area; and wherein second strips of said charge-balance structures, set in said edge area, extend parallel to one another and to said first strips, throughout a whole extension of said first strips.
 3. The device according to claim 1, wherein said strips have a rectilinear extension along one and the same direction, both in said active area and in said edge area.
 4. The device according to claim 3, wherein said structural body is provided in a die made of semiconductor material having a first side, parallel to said direction.
 5. The device according to claim 1, comprising a doped ring region, set within a surface portion of said structural body in said edge area, surrounding said active area; wherein said strips extend through said ring region and into a portion of said edge area surrounding said ring region.
 6. The device according to claim 5, further comprising: a doped region having said first conductivity, set in a respective surface portion of said edge area externally with respect to, and at a distance from, said ring region; and an EQR metal contact set on said structural body in electrical contact with said doped region; wherein said strips extend in said structural body internally with respect to said doped region.
 7. The device according to claim 1, wherein said structural body is provided in a die of semiconductor material, having peripheral edges corresponding to scribe lines and a peripheral portion at the outside of said structural body; and wherein said strips extend over the entire area of said die, including said peripheral portion, up to said scribe lines.
 8. The device according to claim 1, comprising body regions of said second conductivity set in respective surface portions of said active area, each of said body regions being set in a region corresponding and aligned to a respective one of said charge-balance structures and associated with a respective one of said elementary electronic components.
 9. The device according to claim 8, of a vertical-conduction multi-drain MOS type, further comprising: insulated-gate structures set on said structural body at least partially on respective ones of said body regions, and source regions having said first type of conductivity set within said body regions; and metal-contact regions extending on said structural body and in electrical contact with said insulated-gate structures, and said body and source regions.
 10. The device according to claim 1, wherein said structural body is of an epitaxial type formed on a substrate of semiconductor material; and wherein said charge-balance structures extend through said structural body and in part through said substrate.
 11. The device according to claim 1, wherein said strips have a distance of mutual separation that differs in said active area with respect to said edge area.
 12. The device according to claim 1, wherein said strips have a width, in a direction transverse to a main direction of extension thereof that differs in said active area with respect to said edge area.
 13. An edge-termination structure for a semiconductor power device having a structural body of semiconductor material with a first conductivity and provided with an active area housing one or more elementary electronic components; comprising: an edge area of said structural body externally delimiting said active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to said first conductivity, extending through said edge area in order to create a substantial charge balance therein, wherein said charge-balance structures comprise columnar walls extending in strips parallel to one another, without intersections with charge-balance structures present in said active area.
 14. The structure according to claim 13, wherein said strips extend in a rectilinear direction as prolongation of, or parallel to, said charge-balance structures present in said active area.
 15. The structure according to claim 13, comprising a doped ring region, set within a surface portion of said edge area, surrounding said active area; wherein said strips extend through said ring region and into a portion of said edge region surrounding said ring region.
 16. The structure according to claim 15, further comprising: a doped region having said first conductivity, set in a respective surface portion of said edge area, externally to, and at a distance from, said ring region; and an EQR metal contact set on said structural body in electrical contact with said doped region; wherein said strips extend in said edge area internally with respect to said doped region.
 17. A semiconductor structure, comprising: a layer of a first conductivity type having first and second substantially perpendicular sides that form a corner region of the layer; an active region disposed in the layer contiguous with the corner region; and at least one first column having a second conductivity type, disposed in the corner region, and substantially parallel to one of the first and second sides.
 18. The semiconductor structure of claim 17 wherein: the first conductivity type comprises N type; and the second conductivity type comprises P type.
 19. The semiconductor structure of claim 17 wherein: the first conductivity type comprises P type; and the second conductivity type comprises N type.
 20. The semiconductor structure of claim 17 wherein the active region has a shape that is substantially square with rounded corners.
 21. The semiconductor structure of claim 17 wherein the at least one column extends substantially to the other of the first and second sides.
 22. The semiconductor structure of claim 17 wherein the at least one column has an end that is remote from the other of the first and second sides.
 23. The semiconductor structure of claim 17, further comprising at least one second column having the second conductivity type, disposed in the active region, and substantially parallel to the at least one first column.
 24. The semiconductor structure of claim 17, further comprising at least one second column having the second conductivity type, disposed in the active region, substantially parallel to the at least one first column, and extending substantially to the other of the first and second sides of the layer.
 25. The semiconductor structure of claim 17, further comprising at least one second column having the second conductivity type, disposed in the active region, substantially parallel to the at least one first column, and having an end that is remote from the other of the first and second sides.
 26. The semiconductor structure of claim 17, further comprising: at least two first columns having a second conductivity type, disposed in the corner region, substantially parallel to one of the first and second sides, and each substantially having a first width; at least two second columns having the second conductivity type, disposed in the active region, substantially parallel to the at least two first columns, and each substantially having a second width that is different from the first width.
 27. The semiconductor structure of claim 17, further comprising: at least two first columns having a second conductivity type, disposed in the corner region, substantially parallel to one of the first and second sides, and each first column separated from an adjacent first column by substantially a first distance; at least two second columns having the second conductivity type, disposed in the active region, substantially parallel to the at least two first columns, and each second column separated from an adjacent second column by substantially a second distance that is different from the first distance.
 28. The semiconductor structure of claim 17, further comprising a boundary region having the second conductivity type and disposed in the corner region adjacent to a surface of the layer and adjacent to, and at least partially around, the active region.
 29. The semiconductor structure of claim 17, further comprising a boundary region having the second conductivity type and disposed in the corner region adjacent to a surface of the layer and contiguous with, and at least partially around, the active region.
 30. The semiconductor structure of claim 17, further comprising: a boundary region having the second conductivity type and disposed in the corner region adjacent to a surface of the layer and adjacent to, and at least partially around, the active region; and wherein the at least one first column is disposed beneath the boundary region.
 31. The semiconductor structure of claim 17, further comprising: a boundary region having the second conductivity type and disposed in the corner region adjacent to a surface of the layer and adjacent to, and at least partially around, the active region; and wherein the at least one first column extends from the boundary region.
 32. The semiconductor structure of claim 17, further comprising a bias region having the first conductivity type and disposed in the corner region adjacent to a surface of the layer and at least partially around the active region.
 33. The semiconductor structure of claim 17, further comprising: a bias region having the first conductivity type and disposed in the corner region adjacent to a surface of the layer and at least partially around the active region; and a metal contact disposed over the bias region.
 34. A device, comprising: a semiconductor layer of a first conductivity type having first and second substantially perpendicular sides that form a corner region of the layer; an active region disposed in the layer contiguous with the corner region; at least one first column having a second conductivity type, disposed in the corner region, and substantially parallel to one of the first and second sides; and at least one second column having the second conductivity type, disposed in the active region, and substantially parallel to the at least one first column.
 35. The semiconductor device of claim 34, further comprising a body region of the second conductivity type disposed over at least one second column and a portion of the layer adjacent to the second column.
 36. The semiconductor device of claim 34, further comprising: a body region of the second conductivity type disposed over at least one second column and a portion of the layer adjacent to the second column; and a gate disposed over the body region.
 37. The semiconductor device of claim 34, further comprising a drain region of the first conductivity type disposed beneath the layer.
 38. The semiconductor device of claim 34, further comprising: a body region of the second conductivity type disposed over at least one second column and a portion of the layer adjacent to the second column; and a source region of the first conductivity type disposed in the body region.
 39. A system, comprising: a device including: a semiconductor layer of a first conductivity type having first and second substantially perpendicular sides that form a corner region of the layer; an active region disposed in the layer contiguous with the corner region; at least one first column having a second conductivity type, disposed in the corner region, and substantially parallel to one of the first and second sides; and at least one second column having the second conductivity type, disposed in the active region, and substantially parallel to the at least one first column; and an integrated circuit coupled to the device.
 40. The system of claim 39, further comprising: first and second dies; wherein the device is disposed on the first die; and wherein the integrated circuit is disposed on the second die.
 41. The system of claim 39, further comprising: a die; and wherein the device and the integrated circuit are disposed on the die.
 42. The system of claim 39 wherein the integrated circuit comprises a controller.
 43. A method, comprising: forming an active region in a layer of a first conductivity type adjacent to a corner region of the layer; and forming in the corner region of the layer at least one first column having a second conductivity type and being substantially straight.
 44. The method of claim 43 wherein: the first conductivity type comprises N type; and the second conductivity type comprises P type.
 45. The method of claim 43, further comprising forming in the corner region of the layer at least two substantially parallel first columns having a second conductivity type and substantially a same length.
 46. The method of claim 43, further comprising forming in the corner region of the layer at least two substantially parallel first columns having a second conductivity type and different lengths.
 47. The method of claim 43, further comprising growing the layer epitaxially over a substrate.
 48. The method of claim 43, further comprising forming in the active region at least one second column having the second conductivity type and substantially parallel to the at least one first column.
 49. The method of claim 43, further comprising forming in the active region at least one second column having the second conductivity type, substantially parallel to the at least one first column, and having a length different from a length of the at least one first column.
 50. The method of claim 43, further comprising forming in the active region at least one second column having the second conductivity type, substantially parallel to the at least one first column, and having a length substantially the same as a length of the at least one first column.
 51. The method of claim 43, further comprising: forming in the corner region at least two substantially parallel first columns having a second conductivity type and each substantially having a first width; forming in the active region at least two second columns having the second conductivity type, substantially parallel to the at least two first columns, and each substantially having a second width that is different from the first width.
 52. The method of claim 43, further comprising: forming in the corner region at least two substantially parallel first columns having a second conductivity type and each separated from an adjacent first column by substantially a first distance; and forming in the active region at least two second columns having the second conductivity type, substantially parallel to the at least two first columns, and each separated from an adjacent second column by substantially a second distance that is different from the first distance.
 53. The method of claim 43, further comprising forming in a surface portion of the corner region and at least partially around the active region a boundary region having the second conductivity type.
 54. The method of claim 43, further comprising forming in a surface portion of the corner region over at least one of the first columns and at least partially around the active region a boundary region having the second conductivity type.
 55. The method of claim 43, further comprising forming in a surface portion of the corner region integral with at least one of the first columns and at least partially around the active region a boundary region having the second conductivity type.
 56. The method of claim 43, further comprising forming in the corner region adjacent to a surface of the layer a bias region having the first conductivity type at least partially around the active region.
 57. The method of claim 43 wherein forming the at least one first column comprises: forming a substantially straight trench in the layer; and forming in the trench a material having the second conductivity type.
 58. The method of claim 43 wherein forming the at least one first column comprises: forming a substantially straight trench in a first portion of the layer; forming in the trench a material having the second conductivity type; and forming a second portion of the layer over the trench. 